In the manufacture of most semiconductive devices, particularly integrated circuit devices, much of the processing is done on a wafer scale. In such manufacture, a relatively large wafer, for example a wafer of twelve inches in diameter, is treated to a succession of steps to form the various regions of different conductivity type and the assorted connections that define particular integrated circuit devices. After these are formed, the wafer is diced to form a large number of chips, each of which includes an integrated circuit. It is desirable that the integrated circuits formed all be substantially uniform in characteristics.
Generally the manufacture of such devices includes a succession of processing steps, many of which are controlled by masks that have been provided on a top surface of the wafer to localize the effect of the processing steps to particular regions of the wafer. It is important that such masks be appropriately aligned with respect to one another to achieve the necessary precision in the location of the treated regions, particularly if there is to be achieved the desired uniformity between all of the integrated circuits formed in a wafer.
To achieve the desired alignment of the masks used in successive steps of the processing, it is common to use special marks, or indicia, on the masks to print conforming marks on the edges of the wafer and to use such wafer marks for the overlay measurements important for alignment purposes.
Moreover, it is important to detect any significant misalignment early in the processing so that correction can be made timely before further processing.
Currently the measuring process for detecting misalignment uses boxes, typically square or rectangular, of different sizes etched in the wafer as the alignment marks, and uses boxes of different sizes within one another to detect misalignment. This process is limited both by possible asymmetries in the shape of the box and the width of the lines used to define the box, and by the need for the lines to be sufficiently long and wide that they can be measured directly. This can make the box process relatively inefficient when used in the state of the art integrated circuit devices that involve feature sizes of 0.25 microns or less.
The present invention provides a novel technique for determining mask misalignments and is particularly useful in the manufacture of devices that involve feature sizes of 0.25 microns and less.